1. Field of the Invention
The present invention relates to a method of production of a semiconductor device which has an element isolation structure, and more particularly relates to a method of production of a solid-state imaging device, which is capable of realizing a preferable surface flatness when a Shallow Trench Isolation (STI) type element isolation region is formed by a Chemical Mechanical Polishing (CMP).
2. Description of the Background Art
In recent years, a semiconductor device has become highly integrated, and respective elements tend to be significantly refined. Therefore when the semiconductor device is produced, an STI-type element isolation is mainly used, in which the elements of the semiconductor device are isolated from one another by filling shallow trenches, which are formed on a semiconductor substrate, with an insulating material. As a method for forming the STI-type element isolation structure (STI structure), various methods are known, and a typical forming method will be described with reference to FIG. 4. FIG. 4 is a cross-sectional view illustrating a process of a forming method of a conventional STI structure.
For example, on a semiconductor substrate 1 shown in FIG. 4(a), a silicon dioxide film 2 and a silicon nitride film 3, which are insulating materials, are deposited in this order, and the silicon nitride film 3 and the silicon dioxide film 2 are selectively dry-etched by using a resist pattern (not shown), which is formed on the silicon nitride film 3, as a mask. Accordingly, a pattern in which element isolation regions are open is formed in the silicon dioxide film 2 and the silicon nitride film 3. Thereafter, as shown in FIG. 4(a), the semiconductor substrate 1 is selectively dry-etched by using the silicon nitride film 3 as the mask, whereby trenches 4 are formed at all the element isolation regions. In active regions 5 (regions other than the element isolation regions) which are sectioned by the trenches 4, elements are actually formed.
Next, an extra-thin thermally-oxidized film is formed, through thermal oxidation, on inside walls of the trenches 4, and then by using a CVD method, a silicon dioxide film 6, which is the insulating material, is formed on the whole surface of the semiconductor substrate 1 so as to fill inside the trenches 4 with the silicon dioxide film 6. FIG. 4(b) is a cross-sectional view illustrating a process in which the silicon dioxide film 6 is formed. Thereafter, as shown in FIG. 4(c), a pattern of resist 8, which has openings 7 only in such active regions 5 that each has a predetermined area size or larger, is formed on the silicon dioxide film 6. The silicon dioxide film 6, which is exposed through the openings 7, is etched by using the resist 8 as the mask, and then holes 9 are formed in the silicon dioxide film 6 as shown in FIG. 4(d). An interval between one edge of one of the active regions 5 sectioned by the trenches 4 and an edge, being closest to the one edge of the active region 5, of the hole 9 formed in the active region 5, is constant in the respective active regions 5 on the whole region of the semiconductor device, as shown in FIGS. 4(c) and 4(d). Further, an interval between an outer perimeter of one of the active regions 5 sectioned by the trenches 4 and an outer perimeter of the hole region 9 formed in the active region 5 is constant in each of the active regions 5 on the whole region of the semiconductor device.
Next, apart of the silicon dioxide film 6 which is formed on the silicon nitride film 3 and a part of the silicon nitride film 3 are removed by using a CMP method. Accordingly, as shown in FIG. 4(e), the silicon dioxide film 6 remains inside the trenches 4 only, and a structure in which the trenches 4 are filled with the silicon dioxide film 6 is generated. The silicon nitride film 3 is polished together with the silicon dioxide film 6 or independently thereof until the silicon nitride film 3 has a predetermined film thickness. The predetermined film thickness is determined such that a final STI step height does not adversely affect various electrical characteristics. After the polishing based on the CMP method, the silicon nitride film 3 is removed by using thermal phosphate, whereby an STI structure 11 shown in FIG. 4(f) is formed. Thereafter, although not shown in the diagram, the silicon dioxide film 2 is removed by using a hydrofluoric acid series etching liquid, a gate insulating film is formed on the semiconductor substrate 1, and then a conductive film such as a polysilicon film including impurities such as phosphorus and arsenic is deposited on the semiconductor substrate 1 as well as on the silicon dioxide film 6.
In the above-described forming process of the conventional STI structure 11, a case will be considered where the silicon dioxide film 6, on which step heights having projections and depressions are formed by the trenches 4 as shown in FIG. 4(b), is flattened by using the CMP method instead of using the processes shown in FIGS. 4(c) and 4(d). Conventionally, it is known that a polishing characteristic (particularly, a polishing speed depending on a location) changes drastically in accordance with an area and a pattern density of the active region 5, which is a base. Specifically, when the area of the base active region 5 is large, a polishing pressure for pressing the semiconductor substrate 1 onto a polishing pad decreases per unit area, and the polishing speed slows down. Therefore, when the silicon dioxide film 6 is flattened from the state shown in FIG. 4(b) by using the CMP method, the film thickness of the remaining silicon dioxide film 6 becomes thick in such active regions 5 that have large areas. That is, a difference (an STI step height) between a height of an upper surface of the STI structure 11 shown in FIG. 4(f) and a height of an upper surface of the semiconductor substrate 1 is large. The STI step height is defined as a distance d between the upper surface of the semiconductor substrate 1 and the upper surface of the STI structure 11 (the upper surface of the silicon dioxide film 6) as shown in FIG. 5. FIG. 5 is an enlarged diagram of the STI structure 11 in which the silicon dioxide film 2 has been removed from the state shown in FIG. 4(f).
In this manner, when the STI step height is finished as a high step height, a process failure may be caused by exposure/focus abnormalities during various types of mask layer patterning in the production process of the semiconductor device after the STI structure 11 is formed thereon. Further, the conductive polysilicon film remains on a sidewall of the step height portion of the STI structure 11 of the silicon dioxide film 6, the step height portion protruding from the upper surface of the semiconductor substrate 1, and consequently, a leak between the elements may be caused. FIG. 6 is a diagram illustrating a mechanism of the leak occurring between the elements. As shown in FIG. 6(a), the silicon dioxide film 6 is filled in the semiconductor substrate 1, and the step height portion of the silicon dioxide film 6 is wet-etched through a certain process. Accordingly, an overhang shape 12 is formed in the sidewall of the step height portion. A conductive polysilicon film 13, which is used as a gate electrode, is formed thereon (FIG. 6(b)). When the polysilicon film 13 is patterned by anisotropic etching, and when the electrode 14 is formed, an upper portion of the overhang shape 12 acts as an etch stop film, and the polysilicon film remains at a recessed portion of the overhang shape 12 as a residual polysilicon 15. The residual polysilicon 15 causes the leak between the elements at a specific portion on the semiconductor substrate 1. Further, when the STI step height is finished as the high step height, the polysilicon film 13, which extends over the step height portion of the silicon dioxide film 6, stresses the silicon dioxide film 6 so as to press down the silicon dioxide film 6. As a result, various characteristic failures are caused such as a crystal defect at a bottom of the silicon dioxide film 6.
In order to prevent such a problem, and in order that the STI step height is not finished as a high step height, the processes shown in FIGS. 4(c) and 4(d) are performed before the CMP polishing in the conventional method shown in FIG. 4. That is, in the conventional method shown in FIG. 4, the holes 9 are formed in the silicon dioxide film 6 which is deposited on such active regions 5 that each has the predetermined area size or larger. Accordingly, the amount of polishing based on the CMP is preliminarily reduced so as to equalize the polishing speed, and the STI step height is prevented from becoming high.
Further, in order to prevent the STI step height from becoming high, a method different from that shown in FIG. 4 is disclosed in Japanese Laid-Open Patent Publication No. 2004-111527. According to the method disclosed in Japanese Laid-Open Patent Publication No. 2004-111527, a calculation is performed in simulation so as to equalize, in a chip, density and shapes of portions of the silicon dioxide film 6 to be removed, the silicon dioxide film 6 being deposited on the respective active regions 5. In accordance with a result of the calculation, the amount of polishing based on the CMP method is preliminarily reduced and the polishing speed is equalized.
A MOS type solid-state imaging device is a type of a semiconductor device, and includes a pixel portion having arranged thereon a plurality of pixels each having a photodiode which is formed on the active regions and which performs a photoelectric conversion on an incident light, and also includes a peripheral circuit portion which has a plurality of MOS transistors formed on the active regions. In the case of the MOS type solid-state imaging device, a pattern layout per pixel in the pixel portion is as shown in FIG. 7. FIG. 7 is a diagram showing a pattern layout per pixel in the pixel portion of the MOS-type solid-state imaging device. In FIG. 7, 20 denotes a photo-receiving portion composed of the photodiode, 21 denotes a plurality of drive MOS transistors, 22 denotes a floating diffusion, 23 denotes a forward gate electrode which forwards a signal charge generated by the photo-receiving portion 20 to the floating diffusion 22, 24 denotes a contact hole for connecting the floating diffusion 24 to another MOS transistor. The area of the active region to be used in one photo-receiving portion 20 is larger than the area of the active region to be used in the peripheral circuit, which is not shown in the diagram. The pixel portion is composed by arranging thereon several million to several ten million pattern layouts each having the photo-receiving portion 20 shown in FIG. 7. In this manner, the area occupied by the active regions in the pixel portion is larger than the area occupied by the active regions in the peripheral circuit portion.
In the case where the STI structure is formed on the MOS type solid-state imaging device by using the CMP method, the STI step height tends to be high, since the area occupied by the active regions in the pixel portion having the photo-receiving portions 20 is larger than the area occupied by the active regions in the peripheral circuit portion, and consequently the polishing speed in the pixel portion is slower than that in the peripheral circuit portion. Further, even in the pixel portion, from its central portion to peripheral portion, STI step height tends to be biased. Particularly, these tendencies of the high step height and the biased STI step height become significant, when the area of the photo-receiving portion 20 (an area per pixel) is large, when the number of photo-receiving portions 20 arranged on one chip (the number of pixels in the pixel portion) is great, and when the pixel portion occupies a large proportion of the chip. The high STI step height and the biased STI step height in the pixel portion are likely to induce the various characteristic failures, the process failure caused by the exposure/focus abnormalities, or the leak between the elements. In addition, failures specific to the solid-state imaging device may occur such as a saturation characteristic failure, and a black defect and a white defect on an image.
Even if the conventional method shown in FIG. 4 is applied to the above-described MOS type solid-state imaging device, in the conventional method shown in FIG. 4, the holes 9 are formed at constant intervals 10 on the whole region regardless of the pixel portion and the peripheral portion. Therefore, it is impossible to sufficiently prevent the STI step height in the pixel portion from becoming high and to sufficiently suppress the biased STI step height in the pixel portion. Further, the method disclosed in Japanese Laid-Open Patent Publication No. 2004-111527 is directed to general semiconductor devices, and not directed to the MOS type solid-state imaging device. Therefore, even if the method disclosed in Japanese Laid-Open Patent Publication No. 2004-111527 is applied to the MOS type solid-state imaging device, it is impossible to sufficiently prevent the STI step height in the pixel portion from becoming high and to sufficiently suppress the biased STI step height in the pixel portion.
In this manner, the conventional method shown in FIG. 4, and the method disclosed in Japanese Laid-Open Patent Publication No. 2004-111527 have the problem in that it is impossible to sufficiently prevent the STI step height in the pixel portion from becoming high and to sufficiently suppress the biased STI step height in the pixel portion.